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Appliquer la théorie dans la pratique

Développez vos compétences en leadership et en gestion de projet

Travailler sur un projet ambitieux

Lancez votre carrière d'ingénieur

Développez votre réseau en rencontrant des professionnels de l'industrie

Ce qui importe, ce n'est pas seulement ce que vous savez actuellement, mais ce que vous êtes prêt à apprendre.

La motivation, la curiosité, l'autonomie et la proactivité sont essentielles pour nous.

Qu'est-ce qui t'intéresse ?

  Technique  

System Engineering

Model Based Systems Engineering


Type of project: Semester project / Association / Master thesis Participants: 2 - 4 students Section: STI, Minor in Space Tech or System Eng Description: In this project, you will join the CHESS mission at the end of Phase B, and you will contribute in bringing the mission to the next milestone, the PDR. To achieve this goal, you will need to focus on different tasks, mainly ICDs and Risk Analysis. The interface control documents (ICDs) are key to the CHESS mission. They define how the different components, subsystems of the satellite interact with each other to fulfill the mission’s objectives. The higher level architecture and requirements have been defined (mostly), we now need your help to dive into the specifics. The Risk Analysis identifies the possible failures of the system and it defines strategies to mitigate the causes and effects. Tasks:

  • Familiarize yourself with the mission. As a system engineer it is your responsibility to be very well informed and be able to answer most questions or find the answers.
  • Communicate with members from the other poles and universities to get information on the evolution of the subsystems development.
  • Decompose the problem into manageable tasks.
  • Make relevant design trade offs.
  • Adapt to the situation.
  • Be comfortable not knowing something and keep looking.
  • Update the model of the satellite on Valispace (software) when necessary.
  • Most importantly: be curious and enthusiastic about the work and the association! It will make it that much more fun.
Preferred background courses:
  • Space Technologies minor
  • Spacecraft Design and System Engineering
  • Fundamentals of Systems Engineering
  • Or similar knowledge, system engineering mentality




Testing engineer


Type of project: Semester project / Association Participants: 2 - 3 students Section: STI Description: We are starting to work on real satellite hardware. The Assembly Integration and Testing (AIT) phase is one of the most critical phases of any space project. It is not permitted to have issues with the system once the satellite is launched. A small error may result in a mission failure. The AIT allows to make sure that all the subsystems will work as expected in order to have a successful mission. We should have a first version of our On-Board-Computer, the Power system board and the ADCS module Tasks:

  • Understand the roles and functions of the different subsystems which were bought.
  • Create a list of test procedures which need to be performed on all newly bought subsystems.
  • Test each subsystem individually according to this list.
  • Work together with the Flight Software and OBC team.





Power System

Vibration Analysis


Type of project: Association Participants: 1 students Section: STI Description: During the launch, the satellite withstands loads, vibrations that may use or break the structure. An analysis is carried out to derive the fundamental frequencies of the structure and detect eventual problems Tasks:

  • The aim is to continue the project already done to apply ongoing modifications.
Preferred background and skills ::
  • Ansys software




Building of a mass model


Type of project: Association Participants: 1 - 2 students Section: Any Description: To ensure the CubeSat sustains the launch and life in orbit, we have to verify the structure and the subsystems are capable of resisting a certain amount of vibrations and accelerations. In this context, we would like to build a realistic simplified model of the CubeSat and test this model in vibration. This position offers the opportunity to modify the design and build the mass model. Tasks:

  • Machining/3D printing of a mass model




Thermal Analysis/ Control


Type of project: Semester project / Association Participants: 1 - 2 students Section: STI Description: The temperature of the satellite through its life is a crucial matter that has to be studied, to make sure every component stays in its operability range. An finite element analysis has to be carried out in order to check the thermal behavior and if the requirements are respected. Tasks:

  • A first draft was done on Matlab, a FEM analysis must be done to obtain more precise results.
Preferred background and skills ::
  • Matlab / Ansys





Attitude Determination & Control System (ADCS)

Hardware/Software in the loop testing


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, Elec, others Description: The success of the mission depends on extensive testing of all components. Prior to hardware tests, in the loop testing is key. You’ll use two softwares developed by the ADCS supplier to test the ADCS algorithm and operational modes. You will also monitor the states of the ADCS and understand the functionality of the component. Finally you will be engaged in the developement of new ADCS modes tailored to the mission, including the definition of a safe flight mode and verify with simulations the operational capacity of the ADCS and of the newly defined modes. Tasks:

  • Use EOS software to do Software and hardware in the loop testing.
  • Use Cubesupport software to do hardware in the loop and monitor the ADCS states. Develop new operational modes for the ADCS.
  • Manage data transmission between the ADCS computer (microcontroller) and the softwares.
Preferred background courses:
  • C/C++ (EOS and Cubesupport softwares will be introduced to you)




ADCS Test engineer


Type of project: Association Participants: 1 students Section: STI, others Description: Upon the arrival of the complete ADCS module, we will need to test it. Your task will be to define a test protocol, establish the steps to follow, the key aspects to test, the potential failures. The tests will be held in collaborations with other subsystems so you will be ask to work with them. You will have to design the integration of the subsystems into one structure to be tested and the integration of that structure to the test bench (Helmholtz cage). Once the hardware is received you will have to apply this test protocol and report the results of the tests. Tasks:

  • Develop a test protocol for the ADCS components, apply this protocol and report the results.
Background and skills :
  • No particular skills, good understanding of mechanical and electrical systems is needed.




ADCS integration with OBC and Flight software


Type of project: Association Participants: 1 students Section: STI, Systeme de communication, others Description: In flight, the ADCS will be in constant connection and communication with other subsystems, mainly the On board Computer (OBC) and the Flight software. You will be asked to define the communication based on the existing commands. You will have to catalog all of the ADCS commands and communication protocols and ensure that the OBC and FS share the same protocol. You will also work with the test engineer to design the OBC-ADCS joint tests. Tasks:

  • Establish communication protocol between ADCS and OBC/FS. Introduce the ADCS commands to the OBC, ensure the OBC controls the ADCS behavior.
Background and skills :
  • Being able to work with other subsystems. Knowledge in communication protocols is recommended.





Structure

Vibration Analysis


Type of project: Association Participants: 1 students Section: STI Description: During the launch, the satellite withstands loads, vibrations that may use or break the structure. An analysis is carried out to derive the fundamental frequencies of the structure and detect eventual problems Tasks:

  • The aim is to continue the project already done to apply ongoing modifications.
Preferred background and skills ::
  • Ansys software




Building of a mass model


Type of project: Association Participants: 1 - 2 students Section: Any Description: To ensure the CubeSat sustains the launch and life in orbit, we have to verify the structure and the subsystems are capable of resisting a certain amount of vibrations and accelerations. In this context, we would like to build a realistic simplified model of the CubeSat and test this model in vibration. This position offers the opportunity to modify the design and build the mass model. Tasks:

  • Machining/3D printing of a mass model




Thermal Analysis/ Control


Type of project: Semester project / Association Participants: 1 - 2 students Section: STI Description: The temperature of the satellite through its life is a crucial matter that has to be studied, to make sure every component stays in its operability range. An finite element analysis has to be carried out in order to check the thermal behavior and if the requirements are respected. Tasks:

  • A first draft was done on Matlab, a FEM analysis must be done to obtain more precise results.
Preferred background and skills ::
  • Matlab / Ansys





Flight Software

Implementation of the Ardon SoC


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You’ll implement the SoC inside the FPGA which is the core of our OBC. Our SoC will be developed from Briey SoC which will be the basis of your work. The main parts to implement (not pre-existing) are the RAM control, the watchdog and some bitflip correction.
As our SoC will be written in SpinalHDL you’ll have to learn the language. This won’t be a problem given a VHDL background. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • VHDL / SpinalHDL development
Preferred background and skills:
  • VHDL (You’ll learn SpinalHDL quite fast), electronics




PCB development and testing


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You will participate in the testing and development of the on-board computer PCB. The first prototype has been manufactured and needs to be tested! This includes actual hardware testing as well as the programming of some raspberry pi’s to simulate the other components. In addition you will work on the future modifications of the board and assure its functionality. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • Testing and verification of hardware-components
  • Testing and verification of interfaces to other subsystems
Preferred background and skills:
  • Electronics, embedded system design, PCB-design, simple microcontroller programming is a plus.





On-Board-Computer (OBC)

Implementation of the Ardon SoC


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You’ll implement the SoC inside the FPGA which is the core of our OBC. Our SoC will be developed from Briey SoC which will be the basis of your work. The main parts to implement (not pre-existing) are the RAM control, the watchdog and some bitflip correction.
As our SoC will be written in SpinalHDL you’ll have to learn the language. This won’t be a problem given a VHDL background. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • VHDL / SpinalHDL development
Preferred background and skills:
  • VHDL (You’ll learn SpinalHDL quite fast), electronics




PCB development and testing


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You will participate in the testing and development of the on-board computer PCB. The first prototype has been manufactured and needs to be tested! This includes actual hardware testing as well as the programming of some raspberry pi’s to simulate the other components. In addition you will work on the future modifications of the board and assure its functionality. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • Testing and verification of hardware-components
  • Testing and verification of interfaces to other subsystems
Preferred background and skills:
  • Electronics, embedded system design, PCB-design, simple microcontroller programming is a plus.





Telecommunication

Implementation of the Ardon SoC


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You’ll implement the SoC inside the FPGA which is the core of our OBC. Our SoC will be developed from Briey SoC which will be the basis of your work. The main parts to implement (not pre-existing) are the RAM control, the watchdog and some bitflip correction.
As our SoC will be written in SpinalHDL you’ll have to learn the language. This won’t be a problem given a VHDL background. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • VHDL / SpinalHDL development
Preferred background and skills:
  • VHDL (You’ll learn SpinalHDL quite fast), electronics




PCB development and testing


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You will participate in the testing and development of the on-board computer PCB. The first prototype has been manufactured and needs to be tested! This includes actual hardware testing as well as the programming of some raspberry pi’s to simulate the other components. In addition you will work on the future modifications of the board and assure its functionality. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • Testing and verification of hardware-components
  • Testing and verification of interfaces to other subsystems
Preferred background and skills:
  • Electronics, embedded system design, PCB-design, simple microcontroller programming is a plus.





Mission Design

Implementation of the Ardon SoC


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You’ll implement the SoC inside the FPGA which is the core of our OBC. Our SoC will be developed from Briey SoC which will be the basis of your work. The main parts to implement (not pre-existing) are the RAM control, the watchdog and some bitflip correction.
As our SoC will be written in SpinalHDL you’ll have to learn the language. This won’t be a problem given a VHDL background. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • VHDL / SpinalHDL development
Preferred background and skills:
  • VHDL (You’ll learn SpinalHDL quite fast), electronics




PCB development and testing


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You will participate in the testing and development of the on-board computer PCB. The first prototype has been manufactured and needs to be tested! This includes actual hardware testing as well as the programming of some raspberry pi’s to simulate the other components. In addition you will work on the future modifications of the board and assure its functionality. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • Testing and verification of hardware-components
  • Testing and verification of interfaces to other subsystems
Preferred background and skills:
  • Electronics, embedded system design, PCB-design, simple microcontroller programming is a plus.





  Management  

Sponsoring

Implementation of the Ardon SoC


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You’ll implement the SoC inside the FPGA which is the core of our OBC. Our SoC will be developed from Briey SoC which will be the basis of your work. The main parts to implement (not pre-existing) are the RAM control, the watchdog and some bitflip correction.
As our SoC will be written in SpinalHDL you’ll have to learn the language. This won’t be a problem given a VHDL background. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • VHDL / SpinalHDL development
Preferred background and skills:
  • VHDL (You’ll learn SpinalHDL quite fast), electronics




PCB development and testing


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You will participate in the testing and development of the on-board computer PCB. The first prototype has been manufactured and needs to be tested! This includes actual hardware testing as well as the programming of some raspberry pi’s to simulate the other components. In addition you will work on the future modifications of the board and assure its functionality. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • Testing and verification of hardware-components
  • Testing and verification of interfaces to other subsystems
Preferred background and skills:
  • Electronics, embedded system design, PCB-design, simple microcontroller programming is a plus.





Communication

Implementation of the Ardon SoC


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You’ll implement the SoC inside the FPGA which is the core of our OBC. Our SoC will be developed from Briey SoC which will be the basis of your work. The main parts to implement (not pre-existing) are the RAM control, the watchdog and some bitflip correction.
As our SoC will be written in SpinalHDL you’ll have to learn the language. This won’t be a problem given a VHDL background. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • VHDL / SpinalHDL development
Preferred background and skills:
  • VHDL (You’ll learn SpinalHDL quite fast), electronics




PCB development and testing


Type of project: Semester project / Association Participants: 1 - 2 students Section: MT, elec, syscom, others Description: You will participate in the testing and development of the on-board computer PCB. The first prototype has been manufactured and needs to be tested! This includes actual hardware testing as well as the programming of some raspberry pi’s to simulate the other components. In addition you will work on the future modifications of the board and assure its functionality. Feel free to contact michael.linder@epfl.ch for any questions. Tasks:

  • Testing and verification of hardware-components
  • Testing and verification of interfaces to other subsystems
Preferred background and skills:
  • Electronics, embedded system design, PCB-design, simple microcontroller programming is a plus.